diff --git a/recipes/qwen3-8-flash-next-w4a16-2x-cmp-170hx-pp2-mtp5-ple-alexbrandes/recipe.yaml b/recipes/qwen3-8-flash-next-w4a16-2x-cmp-170hx-pp2-mtp5-ple-alexbrandes/recipe.yaml
index 7a20730df..c5dbc799a 100644
--- a/recipes/qwen3-8-flash-next-w4a16-2x-cmp-170hx-pp2-mtp5-ple-alexbrandes/recipe.yaml
+++ b/recipes/qwen3-8-flash-next-w4a16-2x-cmp-170hx-pp2-mtp5-ple-alexbrandes/recipe.yaml
@@ -163,3 +163,4 @@ provenance:
     - 'https://github.com/AlexBrandes/vllm/tree/cmp170hx-qwen38-flash-next'
     - 'https://huggingface.co/Intel/Qwen3.8-Flash-Next-W4A16-AutoRound/tree/4c67bf686b7f7fd386bae6b07ab59e8ff1d5b897'
   notes: "Direct ingest of a 2026-10-17 GitHub-search find (lar-scout card t_67dee659). Recipe repo pinned at HEAD 3f0d60096b3548a5f5449ebca7ab4b0f353bc772 (verified via git ls-remote at ingest; single commit). Engine fork branch cmp170hx-qwen38-flash-next @ 02acf67c verified live (branch tip == pin at ingest). All launch argv transcribed from start.sh at that sha and cross-checked against results/2026-10-17.json launch.args (identical). Checkpoint revision 4c67bf68 + draft-head sha256 5c5461d7... resolved from versions.env as the card instructed. All perf numbers author-reported (T0 submitter) from results/2026-10-17.json three-run medians; no independent re-run. Distinctives vs the site's other 2x170HX QFN rows: pipeline parallel on STOCK PCIe links (no P2P/capacitor mod needed - clee PP3, Morrowmake TP2, Minachist PP2 and mannydelrio PP2 all require link/unlock work), NVMe-mmapped PLE via VLLM_PLE_MMAP (vs staged preadv / shard-direct variants), MTP-5 (siblings use 3-4), BF16 KV + FP32 Mamba state, 262k window (siblings stretch to 384k-1M). Host-tuning caveat: start.sh needs sudo (power limit + readahead + cache drop); HOST_TUNE=0 skips it at ~10% decode cost."
+max_context_len: 262144