{"meta":{"count":2,"page":1,"pages":1,"per_page":12,"applied":{"engine":null,"model":null,"quant":null,"storage":null,"hardware":["rtx-4090","dgx-spark-x3"],"generation":null,"task":null,"tier":null,"tags":[],"vram":null,"search":null,"sort":"updated","featured":false},"origin":"https://localairecipes.com","openapi":"/openapi.json","updated_at":"2026-11-03T13:14:59+00:00"},"recipes":[{"slug":"qwen3-8-flash-next-iq3-s-mtp-on-1x-rtx-4090-llama-cpp-tandem-cpp","title":"Qwen3.8-Flash-Next IQ3_S + MTP on 1x RTX 4090 \u2014 llama.cpp + tandem.cpp MoE expert cache (ewhacc)","summary":"MoE expert-cache offload for llama.cpp via the tandem.cpp patch set: hot experts stay in a GPU expert cache, missed experts are split between CPU compute and an upload into the cache, sized from measured CPU and PCIe speeds; single-user decode is the target. Author's GSM8K first-200 decode numbers on the consumer PC (i5-12400F, 64 GB DDR4, RTX 4090 24 GB): Qwen3.8-Flash-Next IQ3_S + MTP 97.3 tok/s greedy and 96.1 sampled vs llama.cpp f5222f25c 29.8/29.4 (3.3x); gpt-oss-120b 51.5/48.0. REPRO CAVEAT: all numbers are author-self-reported on a repo <24h old with one commit day of history (initial commit 2026-11-02, no releases/tags); nothing reproduced on-box or by a third party - evidence is claimed, tier community. Requires CUDA 13.0-13.4 on Linux (sm_89/sm_120) and 64 GB host RAM for the 78 GiB IQ3_S weights; 1.4-2.1x gains on other MoE models that don't fit VRAM.","tier":"community","beta":false,"generation":"ada","decode_tok_s":73.7999999999999971578290569595992565155029296875,"prefill_tok_s":0,"updated_at":"2026-11-02 09:53:20.10132-07","commit_sha":"543df76dcb783c7c365b8ea88a2d81ed9d36de76","content_hash":"fd8e878ab3aa782deec1708f8b0913a0ee5ea7a7","votes":0,"credit":[{"name":"ewhacc - recipe, patch set and measurements","url":"https://github.com/ewhacc/tandem.cpp"},{"name":"llama.cpp / ggml (MIT)","url":"https://github.com/ggml-org/llama.cpp"},{"name":"MoE expert-split rule adapted from Strata (Niko1221)","url":"https://github.com/Niko1221/Strata"}],"uploaded_by":"localai-recipes","measured":null,"links":{"self":"/api/v1/recipes/qwen3-8-flash-next-iq3-s-mtp-on-1x-rtx-4090-llama-cpp-tandem-cpp.json","alternate":"/r/qwen3-8-flash-next-iq3-s-mtp-on-1x-rtx-4090-llama-cpp-tandem-cpp"}},{"slug":"glm-5-3-flash-exlr8-exl3-experts-on-dgx-spark-tp1-4","title":"GLM-5.3-Flash exlr8 EXL3 experts on DGX Spark TP1-4","summary":"GLM-5.3-Flash exlr8: MoE layers are EXL3-trellis units decoded by the custom exlr8 MoE kernel; dense linears stay FP8/NVFP4. One release carries three expert widths (k2/k3/k4 = 2/3/4 bpw), chosen at boot via VLLM_EXLR8_WIDTHS. Reference topology TP=4 on four GB10 boxes; TP=1 serves the whole model (~87 GiB) on one 128 GB DGX Spark / ASUS GX10 via tp1.yaml plus a distinct MENTAT_GROUP. TP=2 and TP=3 also measured. 2026-10-19, clocks TP-locked at 2200 MHz: decode code 128.0 tok/s, prose 72.5 at TP=4; 53.0 / 29.5 at TP=1; prefill 4,393 tok/s at 8K, 4,190 at 32K. Trade vs the shipping NVFP4 build: decode +3-8%, NLL equal or better, KV pool ~+15%, prefill 7.7% lower at Second 1x-Spark GLM-5.3-Flash lane: not the VQ Q4_K GGUF lane (/r/glm-5-3-flash-vq-q4-k-1x-dgx-spark-1m-ctx-jlfn), and not a fork of the 2x ATLAS build (/r/glm-5-3-flash-nvfp4-on-2x-dgx-spark-atlas-rc4-2-tp2-dflash2-1m) whose NVFP4 Flash base this stack overlays.","tier":"community","beta":false,"generation":"blackwell","decode_tok_s":65.2000000000000028421709430404007434844970703125,"prefill_tok_s":3438.5,"updated_at":"2026-10-31 11:51:31.886893-06","commit_sha":"e576a851c441c37ac2fb42dfa0188eef41f910e0","content_hash":"237f8f6570a37cb5ddb895edbae6d611ef23660e","votes":0,"credit":[{"name":"kindlingai","url":"https://github.com/kindlingai/glm-5.3-flash-exlr8-gx10"},{"name":"nvidia","url":"https://huggingface.co/nvidia/GLM-5.3-Flash-NVFP4"}],"uploaded_by":"localai-recipes","measured":null,"links":{"self":"/api/v1/recipes/glm-5-3-flash-exlr8-exl3-experts-on-dgx-spark-tp1-4.json","alternate":"/r/glm-5-3-flash-exlr8-exl3-experts-on-dgx-spark-tp1-4"}}]}